In electronic circuits that use processor(s) such as general purpose microprocessors, digital signal processors, and the like, embedded in an Integrated Circuit (the embedded processor(s) also hereinafter referred to as embedded processor(s)), a few of the functions that need to be tested are the reset function of the embedded processor(s), as well as the initial power up reset of the entire electronic circuit. The embedded processor(s) reset function needs to be tested while the processor is actively executing a program, such as a test program, in order to fully test the operation of the reset function.
The functionality of the embedded processor(s) needs to be verified to ensure that the embedded processor core(s) functions as specified when operated in the Integrated Circuit, for example, a Field Programmable Gate Array (FPGA). Processor functionality is typically verified using test programs running on the processor(s). When the FPGA is powered up, the embedded processor core is placed in a reset mode by the test program while the FPGA is configured. Once the FPGA configuration is completed, the power up reset signal to the processor is de-asserted and the embedded processor starts fetching instructions from a test program that is loaded onto the processor and commences executing the instructions to verify various processor functions.
A typical processor will have a feature such as a Watch Dog Timer (WDT) that can be programmed so that the processor can be reset when the WDT times out. The problem with this approach in an embedded system environment is that after the test program resets the embedded processor, the test program reboots and starts executing again from the beginning. Thus, a need exists in the art for a way to prevent an embedded processor from executing a test program in an infinite reset loop and for a test program to verify in a self-checking fashion that it indeed resets the embedded processor.